Sample and Hold

Sample-and-hold (SH) is part of the analog-to-digital conversion process. The core circuitry of an ADC requires a static input voltage during the small interval of time that is needed to convert the analog signal into a digital value. The SH device (or block in the case of an integrated circuit) provides that static input to the ADC while the actual input signal continues to change.
Typical SH circuits use operational amplifiers (op-amps) with very large input impedances to sense the input voltage. The op-amp's low output impedance drives an output storage capacitor. The storage capacitor is intended to maintain that voltage over the duration of the sampling process.
There are several key metrics for evaluating SH performance. Acquisition time refers to the length of time the SH circuit requires the input to be actively connected to the op-amp. Shorter is better because if the input is changing during acquisition, the sampled value will be an average of the input signal over the acquisition time. Gain and offset error refer to the op-amp characteristics, and once again the smaller these values are, the better the SH performance. Finally, droop error characterizes how much the output voltage will change over the hold period due to charge leakage from the storage capacitor. Read more Read less